The R8051XC2 configurable processor core implements a range of fast, 8-bit, microcontrollers that execute the MCS®51 instruction set.
The IP core runs with a single clock per machine cycle, and requires an average of 2.12 machine cycles per instruction. Dhrystone 2.1 tests show it to run from 9.4 to 12.1 times faster than the original 8051 at the same frequency. Representative 90 nm ASIC results have reached 430 MHz, for an effective speed-up of 400 times over 80C51 chips.
The core has a rich set of optional features and peripherals. Designers can choose from several versions, including the easy-to-configure full version with all options included; a custom, non-configurable version with options specified at purchase; and pre-packaged versions with different sets of options and degrees of configurability.
All versions of the core benefit from power-saving architectural efficiency—the R8051XC2 is 10% better in milliwats/DMIP than our previous generation—and various power-management options are available. System development is facilitated through the EASE native on-chip debugging option and support by Keil’s C51 integrated development environment.
This new product builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking, synchronous reset, and no internal tri-states. Representative 90nm ASIC results show the core to be conservative in its use of space, requiring just 8,000 to 71,000 gates.
- Fully compatible with the MCS® 51 instruction set
- Single clock per cycle and efficient architecture for up to 12.1 times the performance of original 8051
- Fewer machine cycles means lower average power usage in most applications
- Extensive set of optional features and peripherals: choose configurable or less-expensive fixed versions
- EASE Debugging option: On-Chip Debug Support (OCDS) block that interfaces through IEEE1149.1 (JTAG) port; external debugging pod with JTAG and USB; and debugging software with interface to Keil C51 tools
- Options and Peripherals
- Full user-configurable version includes all of these; other versions include a subset (see Versions).
- External Memory Interface:
- Addresses up to 8 MB of Program and Data Memory each (when using memory banking)
- One, two or eight Data Pointers for fast data block transfer
- Additional Arithmetic Unit supports data pointers, auto-increment/-decrement, and auto-switch
- Supports external DMA controller through HOLD function
- Program memory write mode
- Direct Memory Access (DMA) Controller:
- Up to eight independent channels
- Read/Write Access to all memory spaces (incl. SFR)
- Linear addressing (up to 8MB)
- Address auto-increment/decrement
- Synchronous/asynchronous Mode
- Software/Hardware Triggers
- Multiplication-Division Unit:
- 16 x 16-bit multiplication,
- 32/16- and 16/16-bit divisio,
- 32-bit normalization and L/R shifting
- Special Function Registers Interface:
- services from 43 to 119 external SFRs
- Interrupt Controller:
- Four priority levels with eighteen interrupt sources, or
- Two priority levels with six sources
- Input/Output Interfaces
- Parallel Ports: up to four 8-bit Input/Output ports
- Serial 0 interface: Full-duplex serial interface (80C51-like), Equipped with an additional baud rate generator
- Serial 1 interface: an asynchronous-only version of Serial 0
- SPI Master/Slave interface
- I2C™ Master/Slave interfaces: one or two
- Timers and Counters
- 16-bit Timers/Counters: Timers 0 and 1: 80C51-like simple timers; Timer 2: 80C515-like, operates as timer, event counter or gated timer
- Watchdog Timer: 15-bit programmable
- Power Management Unit with power-down modes (IDLE/STOP) Verification:
- all versions include sophisticated self-checking Testbench (Verilog versions use Verilog 2001) with CPU behavioral model, memory models, and more.
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Easy-to-use configuration tool (with configurable versions)
- An example chip implementation, which uses the core in a sample system
- Sophisticated self-checking HDL Testbench including everything needed to test the core (Verilog versions use Verilog 2001)
- Simulation script, vectors, and expected results
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including detailed specifications and a system integration guide