Digital image acquisition (display) devices, both static and video, produce (need) image samples on a line-by-line/pixel-by-pixel basis; a scheme well known as raster scan. On the other hand many image processing-transform algorithms work on a block-by-block basis. Typical image processing examples of this kind include types of the N x M image processing filter matrices such as smoothing filters, edge detection filters, noise reduction filters etc. In the image transform context a well known example is the 2D-Discrete cosine transform (2D-DCT), especially the 8x8 block 2D-DCT, found among others in the MPEG video compression and in JPEG image com-pression.
Streaming applications and applications that cannot afford a full frame buffer but still wish to use such a block-by-block based algorithm face the need of on-the-fly conversion from raster scan pixels to blocks and vice versa. Our RBBRC Raster-to-Block & Block-to-Raster core is designed to be the perfect standalone and on-the-fly conversion solution for the JPEG image compression algorithm. Its use can be extended also to other applications that need to work on rectangle pixel blocks.
The RBBRC is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design is strictly synchronous with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward.
Features
- Raster scan to JPEG MCU order
- JPEG MCU order to raster scan
- Full streaming support
- Supported component sampling factors
- 4:4:4
- 4:2:2
- 4:1:1 (horizontal)
- 4:4:4:4 (CMYK)
- 1:0:0 (grayscale)
- 8 bit sample precision
- Padding; De-padding
- Up-sampling
- Sustained per cycle operation
- Does not insert extra idle cycles and compensates host stalls – perfect for video encoders and decoders
- High throughput – over 100 MSamples on FPGA platforms
- Standalone operation
- Fully stallable interfaces
- Low power standby mode – global synchronous register enable
- Hardware proven
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
Deliverables
- VHDL or Verilog RTL source code
- Post-Synthesis EDIF (netlist release)
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- Simulation and synthesis scripts
- Place & Route scripts (netlist release)
- Documentation & Design Support
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