The Arasan 16550D High Speed UART IP core is a16550-compliant Universal Asynchronous Receiver/Transmitter (UART) with FIFO or expanded FIFO. The UART performs serial to parallel conversion of data received from the serial interface, and parallel to serial conversion of data received from the CPU interface. Both character and FIFO
modes are supported.
- Programmable Serial Interface Characteristics :
- 5,6,7,8 bit characters
- Even, odd parity bit generation and detection.
- 1, 1 1/2, 2 Stop bit generation.
- Independently controlled Receive, Transmit, Line Status Interrupts.
- Programmable Baud Generator divides any clock input by 1 to 65535 and generates the clock * 16.
- Line Break Generation and Detection.
- MODEM Control Functions. (CTS, RTS, DSR, DTR, RI and DCD ).
- Loop Back Checking.
- Independent Receiver clock Input.
- Verilog RTL
- Synthesis and Test Scripts
- Test Bench
- Behavioral models
- Software drivers
- Evaluation board