Aizyc SD 3.0 Host IP is compact, low power and highly configurable IP. It is easy to integrate and a very cost effective IP.
Aizyc IP is fully compliant with the standard SD Host Controller Specifications Version 3.0 and SD physical Layer Specifications Version 3.01.
Aizyc SD 3.0 Host IP provides supports for various system interfaces – VCI, AHB and OCP. Number of slots[1/2] available is also configurable. It provides UHS-I modes of operation - DS, HS, SDR12, SDR25, SDR50, SDR104 and DDR50.
The IP core is portable to either an ASIC or a FPGA. It has been validated on Xilinx Spartan 3 platform.
Along with the IP core, we will also provide complete test environment
with constraint randomized test cases. Our full support will be available to help you in complete integration.
- Compliant to SD Host Controller Specifications version 3.00
- Compliant to SDIO specifications version 3.00 draft 1.01
- Conforms to SD Physical Layer Specifications version 3.01
- Supports following UHS-I modes of operation
- DS – Default speed mode up to 25MHz 3.3V signalling
- HS – High Speed mode up to 50MHz 3.3V signalling
- SDR12 – SDR up to 25MHz 1.8V signalling
- SDR25 – SDR up to 50MHz 1.8V signalling
- SDR50 – SDR up to 100MHz 1.8V signalling
- SDR104 – SDR up to 208MHz 1.8V signalling
- DDR50 – DDR up to 50MHz 1.8V signalling
- Supports SPI, 1-bit and 4-bit SD modes
- Supports single slot. Option to support multiple slots
- Supports clock tuning
- In-built clock divider
- Support CRC7 and CRC16 generation/ checking
- Supports IO52 and IO53 commands for SDIO cards
- Supports Read Wait Control and Suspend/Resume operations
- System Interface – VCI, AHB, OCP
- Supports SDMA and ADMA
- Configurable FIFO depths
- Supports stop at block gap
- Support interrupt
- Supports 1.8V, 3.3V and 3.0V operation. Chip pads are 1.8V. Board level solution is required to support 3.3V and it is controlled by a GPIO pin
- Scalable IP Core
- Compact Design
- Portability : ASIC, FPGA
- Validation on Xilinx
- Continuous support during integration, design and verification
- Synthesizable Verilog RTL
- Test bench and exhaustive Test cases
- Synthesis constraints and script files
- Documentation – User Manual, Verification plan , Validation Report,
- Synthesis, DFT and integration Guidelines
- Sample AHB Slave Driver