The USB 2.0 HSIC PHY IP is a cost effective and lower power replacement for a standard USB 2.0 PHY in applications where USB is being used on a single printed circuit board. It is becoming increasingly attractive to use USB as a high speed chip-to-chip interconnect within a product where low cost and low power are required. However, because USB was designed to enable hot-plugging of peripherals over cables up to 5 meters in length, certain power and implementation features are not required for chip-to-chip interconnect solutions. To better meet the needs of a USB chip-to-chip interconnect, HSIC accomplishes this by removing the analog transceivers, thus reducing complexity, cost and manufacturing risk.
- High-Speed 480Mbps data rate only
- Source-synchronous seriel interface
- No power consumed unless a transfer is in progress.
- Maximum trace length of 10cm
- No hot Plug-n-Play support, no hot removal/attach
- Signals driven at 1.2V standard LVCMOS levels
- Designed for low-power applications
- No high-speed chirp protocol, the HSIC interface is always operated at high-speed
- HSIC host or peripheral can be powered in any order
- The full IP package complete with:
- Test environment
- User Guide
Block Diagram of the HSIC USB 2.0 PHY IP