The HyperDrive Multi-port DDR2 Memory Controller IP Core brings FPGA based hardware DDR2 designs to a whole new level of performance. Built around a new DDR2 state machine memory controller which operates at half the DDR2 clock rate, the design optimizes the performance of both the FPGA fabric and I/O structures enabling 400 MHz DDR2 (800 Mbps) performance in a Stratix II, III or IV device.
The HyperDrive Multi-port DDR2 Memory Controller IP Core supports burst memory RD/WR access cycles and handles all memory tasks, including initialization and refresh cycles. The core integrates: a burst DDR2 memory controller core, a port arbitrator and an intelligent look-ahead FIFO controller into one easy-to-use core.
The core supports up to ten independently clocked, full-rate streaming-data devices operating from one shared high bandwidth memory system. With a few clicks of a mouse and within minutes, using the intuitive GUI interface, designers can create a multi-port system, a design task which would normally take several man-months of effort!
- 400 MHz/ 800 Mbps DDR2 memory performance
- Up to 10 local bus native RD or WR ports
- Configurable FIFO depth: 16 to 2048 bytes
- Memory data width: up to 128 bits
- Local bus width from 8 to 128-bits
- Integrated PHY
- Intelligent DDR2 burst caching controller minimizes wait-states
- Layout independent DDR Round-Trip capture scheme
- Requires only single PLL with 4 clock outputs
- Multiple time domain clocking
- Hamming ECC single bit error correction and double bit error detection
- Configuration GUI streamlines design process
- Supports TimeQuest timing analyzer to ensure timing closure
- Supports Stratix II/II-GX, III, IV/IV GX and Arria GX/II-GX devices
- Source-synchronous Data Capture
- The HyperDrive Multi-port Memory Controller uses DQS source-synchronous clocking to capture DDR2 data independently from each memory device. This relaxes timing margins across the memory interface increasing performance by 20% or more. It also has the added benefit of requiring only one non-dedicated PLL.
- This DQS data capture technique, eliminates data round-trip dependent time constraints and the effects of PCB trace length variations between chips, freeing the memory design task from PCB layout parameters. Additionally, it removes the need for auto-calibration training cycles, the constraints of devices-to-device timing skews, and the impact of DQS jitter and clock buffer delays. With the application of source-synchronous clocking to memory design, Microtronix has greatly lowered the barriers to building high performance and wide data bus DDR2 memory systems.
- Synopsis TimeQuest support ensures timing closure
- ModelSim/VHDL precompiled simulations library
- On Die Termination (ODT) improves signal integrity
- IP Core License includes 1 year of updates
- Altera OpenCore Plus evaluation