CC1322INPLL-T40LP is ideal for generating the analog sampling frequencies at a low accumulated rms jitter of 15pS. Its low period-jitter makes it suitable for systems implementing high-speed data-transfers. Its high VCO frequency of 2GHz makes it versatile in supporting a variety of input frequencies to produce a given output frequency. The input-divider, feedback-divider and output divider are all independently programmable, providing flexibility.
- Integer PLL with low accumulated jitter, suitable for analog sampling applications
- Long-term jitter (accumulated rms): 15pS
- High VCO frequency of around 2GHz provides flexibility in input and output frequency combinations
- Outputs: 80MHz and 160MHz output for ADC and DAC sampling respectively. 44MHz average frequency output for clocking digital circuits Can be customized to other output frequencies
- Power Supply 2.25V-3.6V 1.1V 5%
- Compact Foot-print: Contact email@example.com
- Low-power: Contact firstname.lastname@example.org
- TSMC 40nm 1P6M LP process, with 2.5V IO MOS
- This PLL can be used to generate clocks for multiple standards and supporting multiple input and output frequencies. This is made possible by the high VCO frequency. The jitter is low, making it useful for analog sampling applications and high-speed interfaces. The high PSRR and the low-power are other useful aspects.