Implements a pin-compatible replacement for the Intel® 80C188EC chip.
It is Identical to the C80186EC but has an 8-bit rather than a 16-bit system interface for compatibility with 8-bit architectures. A single-chip, high-performance, 16-bit microcontroller, the core executes the widely-known instruction set of Intel 80c86 or 80c186 devices. It has an extended peripheral set with three timers, two serial units, a watchdog timer, two universal interrupt controllers (8259a) and four DMA channels.
Compatibility with the original chip was ensured using hardware modeler-based reverse engineering. Software written for the original chip should execute on the C80188EC with little or no additional effort. A set of flexible outputs makes it easy to ensure pin-to- pin compatibility using current ASIC or FPGA fabrication technologies, making obsolete part replacement straightforward and cost-effective for either low- or high-volume applications.
The microcode-free core design is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset; therefore scan insertion is straightforward. Customers have successfully used this core to replace obsolete chips.
Features
- Control Unit:
- 9-level deep and 1-byte wide instruction queue
- Independent instruction execution stages allow instructions to overlap
- Arithmetic Logic Unit:
- 16-bit arithmetic and logical operations
- Boolean manipulations
- 16 x 16-bit multiplication and 32-/16-bit division
- Memory Interface:
- compliant with the 80c1886ec device
- 20-bit addressing space
- 1MB memory space divided into 64KB logical segments
- Internal and external control of the length of memory access to instruction and data
- 64KB IO space
- Chip Select Unit with ten chip select outputs for use with memory devices
- Peripheral Control Block:
- 128 16-bit wide words predefined for peripherals control
- Programmable into memory or IO space
- Power Management Unit enabling clock division by 1,4,8, 16, 32 and 64 factors
- Three 16-bit Timers/Counters
- Watchdog Timer
- Direct Memory Access (DMA) Controller:
- Four separate, full-functional DMA channels
- External transfer initiation by DRQn pins
- Linear access to 20-bit memory addressing space
- Two USART Peripheral Interfaces in full duplex mode:
- Synchronous and asynchronous transmission
- Full-duplex operation
- 7-, 8- or 9-bit data transfers
- Odd, even, or no parity
- Clear to send feature in transmission
- Double buffered TX/RX
- Programmable Interrupt Controller:
- Two internally cascaded 8259a interrupt controllers
- Nine external interrupt lines, including NMI
- Seven internal interrupts generated by peripherals
- Refresh Control Unit
- Strictly synchronous design with no internal tri-states
Deliverables
- VHDL/Verilog source code (soft core) or a post-synthesis EDIF netlist (firm core)
- Example CHIP80188EC module. This chip level design uses the C80188EC IP core and illustrates how to build the module that is the pin replacement of the 80c188ec device
- Extensive stand alone VHDL Testbench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis (soft) or place and route (firm) script
- Comprehensive user documentation, including detailed specifications and a system integration guide
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