The SUPI4-IP is the conversion of the new INTERBUS slave protocol chip SUPI4 in an FPGA. This next generation of the INTERBUS industry standard meets both current and future automation requirements with new and improved system functions. In addition to supporting new system features, it also optimizes interface technology. With the SUPI4, INTERBUS interfaces can be implemented faster, easier, and more cost-efficiently.
- Compatible with the SUPI4
- Connection to Altera’s NIOS II
- Supported by SOPC Builder
- Compatible with the Interbus Master from Phoenix Contact
- Compatible with the entire Altera product line
- SUPI4-IP dimensions
- <6000 LEs and 6k memory bits in the Altera Cyclone II product line
- <3000 ALUTs and 6k memory bits in the Altera Stratix II product line
- The SUPI4-IP includes all of the features of the SUPI4. It provides a connection to Altera’s NIOS II; alternatively, other microcontrollers can also be integrated into the system. This allows the combination of the SUPI4, the governing microcontroller, and application-specific logic in one chip.
- Evaluation Package:
- Complete design with Altera’s NIOS II and peripherals for temporary testing in EBV Cyclone
- Evaluation Board DBC2C20.
- Production Package:
- MAZeT GmbH provides a simple testing program and documentation.
- MAZeT Support
- System design
- Software and driver support