iW-DMA Controller

Features

• Compatible to 8237
• 24-bit length address register
• 16-bit length count register
• 4 independent DMA channels
• 4 clock / 1 bus cycle
• Byte transfer / word transfer selectable
• Supports three transfer modes (Single, Demand, Block)
• Two bus modes (Bus release, Bus hold)
• DMA request maskable on an individual channel basis
• Software DMA request in uPD1037 mode
• Auto initialization function
• Two kinds of channel priority order (Fixed & Rotating)
• Casacding capability

Benefits

• Uses to reduce the load of the CPU
• Configurable for ease of use

Deliverables

• Technical Specification
• RTL Verilog Synthesizable Code
• Comprehensive Test Environment
• Technical Support and Maintenance