The Evatronix JPEG2000-4K is a fully compatible implementation of an ultra-high performance image encoder based on the ISO/IEC 15444-1 compression standard targeted for both FPGA and ASIC applications.
The encoder enables encoding of any custom frame size up to 16K. It supports real-time processing of digital cinema resolutions such as 2048x1080 (2K), 3840 x 2160, 4096 x 2160 (4K). Moreover, the IP core is capable of real-time encoding of 3D image-video material. Number of simultaneously processed channels (views) depends on the resolution.
The Evatronix JPEG2000-4K is flexible with respect to input image format, including different color spaces (RGB, YCbCr) with up to 16-bits per sample and various component sub-sampling schemes (4:4:4, 4:2:2, 4:2:0, grayscale).
Three very efficient 2D-DWT engines and six EBCOT TIER-1 channels operating in the ultra-high performance, but still single-core JPEG2000-4K architecture, provide enormous compression speed up to 600 MSamples/s. Higher performance can be obtained by multiple cores integration. Maximum frame rates achievable in a single core are: 1080p100, 3D 1080p50, 2Kp96, 3D 2Kp48, 4Kp24.
- Support for 1-3 component images
- Configurable color depth: 8, 10, 12 and 16-bits per component
- Different component sub-sampling schemes: 4:4:4, 4:2:2, 4:2:0, 4:0:0
- Custom, programmable input image resolution up to 16Kx16K
- Maximum codestream bitrate: 600 Mbit/s
- JPEG 2000 standard compliant codestream
- JP2 file format
- Both lossless and lossy compression modes supported
- Flexible tile size, limited by input image resolution and number of decomposition levels
- Full-frame encoding (no tiling) up to 2048x2048 resolution
- Programmable code-block sizes: 16x16, 32x32, 64x64
- Support for different types of external memory: SRAM, SDRAM, DDR2/DDR3 SDRAM memories
- DCI 2K/4K/8K image resolutions support
- Real-time 3D video compression
- Ultra-high compression speed
- The best compression quality
- Lossless and lossy encoding mode
- Flexible input image format
- Support for color depth up to 48 bits per pixel
- Customizable design: ASIC 28-130nm, Xilinx Virtex-5/6/7, Spartan-6, Altera Stratix IV/V and other FPGAs
- VHDL source code for the JPEG2000-4K IP Core
- Synthesis support (Synopsys®, Cadence®) with a complete set of synthesis scripts
- Simulation support (Mentor Graphics®, Cadence®) with a set of scripts and macros
- Extensive HDL Test Bench
- Set of expected results
Block Diagram of the JPEG 2000 Image Encoder for DCI 4K and 3D Real-time Applications