JPEG / MJPEG Hardware Compressor / Encoder (100 embedded quality levels)

Features

• Baseline DCT compression according to JPEG ITU-T T.81 | ISO/IEC 10918-1 with JFIF 1.02 standard file header.
• On-the-fly selectable quality level/compression ratio from 1 to 100 before every compression (equivalent to SW solutions: IJG's JPEG lib., GIMP, IrfanView, etc.).
• Selectable chroma subsampling (4:4:4, 4:2:2 vert., 4:2:2 horiz., 4:2:0).
• Unlimited input image size (up to 64K x 64K as per JPEG spec.).
• Continuous data mode (input one image after another).
• Data input: 24 bits RGB pixels through DMA engine.
• Data output: 8 bits bus sequential output of the final JPEG image file's bytes.
• Optional modules: EXIF support, Motion JPEG (MJPEG) support, Restart marker support.
• Throughput: 2 compressed pixels every 3 clock cycles (up to 135 Mpix/s in a Virtex-5 FPGA).

Benefits

• Compared to other JPEG IP cores this is the fastest and most versatile solution.
• It goes further than others in terms of speed, compressing up to 65 fps at HD1080 resolution (1920x1080 pix).
• It allows a larger versatility thanks to its in built quality selection capability, so you can change the compression ratio and chroma subsampling before every image compression just by changing one register.
• No need for any external components.
• Tailored to your very needs: Look for your part number at the core's website in order to know the exact resource requirements and maximum frequency for your FPGA part.

Deliverables

• Full technical support up to succesful client integration
• Synthesis scripts and results
• Complete Testbench
• Instantation Template
• Documentation and design examples

Video Demo of the JPEG / MJPEG Hardware Compressor / Encoder (100 embedded quality levels)

VSIENG JPEG Codec Demo