ChipWare: Parameterized word-length counter that implements a linear feedback shift register (LFSR) with a dynamic count-to flag. An LFSR counter runs faster than a binary counter in synchronous systems because only the first bit is calculated and the remaining bits are shifted. The counter is loaded synchronously with the data in the data port when load is asserted. When count reaches the value of count_to, tercnt is asserted for one clock. When the count enable pin, cen, is high, the counter is active. When cen is low, the counter is disabled and count remains at the same value. The reset signal is an active low, asynchronous reset signal. When reset is asserted, the counter output is 0. The count port is an output port, ranging from width-1 to 0. A value of 2width-2 (11...11) is an illegal state. Therefore, the counter stops at 11...11. The tercnt is an output terminal count signal that is active high. The signal tercnt goes high for one clock cycle to indicate the number of clock cycles that have elapsed between the count and count_to value.
- This IP is available as part of Cadence Encounter RTL Compiler XL