The Fractional-N Digital PLL is ideally suited for applications that require low-power operation and demanding jitter performance in a very compact area, such as in high-speed digital clocking, ADC clocking, SERDES, and other wireline applications.
This digital PLL employs patented and proven low-power techniques for high-resolution time-to-digital conversion along with a stable and precise oscillator to allow for state-of-the-art high-speed performance in a miniature footprint.
The CAT-PLF-CCC-40 operates from a 1.1V supply and supports output frequencies up to 4GHz with input frequencies up to 100MHz. Manufactured in a state of the art 40nm CMOS process, the robust CAT-PLF-CCC-40 has very low jitter, low power operation (actual numbers available with NDA), and an excellent lock time of less than 50μs which makes it ideal for ultra-low power system applications.
Many options are offered on the PLL, including a parallel or serial programming interface, an increased range of reference and output frequencies, and multiple outputs with precise delay spacing. The standard PLL is optimized for ease of use and integration in complex SoCs.
- Single 2-4GHz phase-locked loop
- Excellent short and long-term jitter
- Tiny silicon footprint
- Fast settling time
- Option of divided outputs or reference frequencies
- Fully characterized hard GDS (gds2)
- Spectre netlist and behavioral models (to enable SoC simulations)
- Abstract view at layout level (for top level connectivity)
- Integration application notes and support
Block Diagram of the Fractional-N Digital PLL in 40nm CMOS