CC150900DLL-C65LPE is ideal for generating low jitter programmable delay suitable for DDR applications. The DLL supports an input range of 150MHz – 900 MHz and can generate a delay of upto 50% of the input clock period with programmable step size of with low period jitter of 2% p-p at the final clock output. This makes it suitable for DDR applications.
- Multiphase DLL with low jitter suitable for DDR applications
- Peak-to-peak period jitter of 2 % at the final clock out.
- Low static phase offset of 50 ps
- Supports a wide input frequency range of 150MHz-900MHz
- Programmable delay of upto 50% of the input clock period available with delay adjustment step size of 1% of the input period
- Core Cell Area: Contact firstname.lastname@example.org
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- Chartered 65nm LPE process