Synopsys' DesignWare® ARC™ Sound 211SFX configurable core is a full-featured, mid-range embedded core with best-in-class speed, die area and power characteristics. It is designed as a complete core solution for system-on-chips (SoCs) targeted at consumer, networking, automotive and other cost-sensitive markets. The DesignWare ARC 211SFX core's flexible, configurable memory architecture makes it ideal for RTOS-based applications. Powerful DSP options enable it to perform more functions, eliminating separate logic or DSP blocks from the SoC. Optionally, custom instruction extensions may be incorporated to achieve application performance levels unattainable with fixed architecture cores. The DesignWare ARC Sound 211SFX DSP supports a broad offering of audio coding formats. Architecture:
5-stage instruction pipeline
32-bit data, instruction and address busses
XY memory and address generators eliminate memory fetches and additional CPU cycles
Dual 16x32 and optional 24x24 MAC
Zero overhead looping
Audio-optimized DMA unit
Configurable single-cycle instruction closely coupled memory (ICCM): 1KB - 512KB
Configurable single-cycle data closely coupled memory (DCCM): 2KB - 256KB
Configurable instruction cache: 2KB - 32KB
Configurable data cache: 2KB - 32KB
Software Support:
MP3
Windows Media Audio 9 / 10Pro
FLAC
Vorbis
Monkey’s Audio
Dolby Digital (AC-3)
Dolby Digital Plus (E-AC-3)
aacPlus v1, v2 / HE AAC
MPEG Layer I/II
LC SBC
MPEG MP3
MPEG-4 AAC-LC
MPEG-4 AAC-LC
G.726
Sample Rate Conversion
DesignWare Sonic Focus audio post-processing audio enrichment
Features
- Minimal core with cache configuration starts at 28,500 gates
- Fully configured inc
- DSP Inst., caches, ICU, etc at between 40-60K Gates
- Floating Point Extentions (Single and Double precission)
- Verious Hardware Multipliers and Dual Multiply Accumulation (Dual MAC) Units (Dual 16x16, Dual 16x32, 24x24, 32x32, etc...)
- Power consumption in 90-nm between 24-50 uW/MHz
- 1.3 DMIPS/MHz
Benefits
- A highly configurable and extandable RISC core
- Extendable with Customer acceleration logic and User-defined instruction
- Caches & closely coupled (single-cycle) memories
- 16-/32-bit Instruction Set Architecture for the smallest code size
Deliverables
- Delivered as synthesizable RTL source code (Verilog®), the DesignWare ARC 625D configurable core is fully compatible with industry standard design methodologies and tool flows
- ARChitect Correct-by-Construction Configuration GUI
- ARChitect Core Extensions Configuration GUI
- Standard & Custom Training
- Support & Maintenance
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