Camera Processor for Mobile 3D and High Resolution Still Picture and Video Applications

The camera processor IP cores are a complete family of low-power video and still picture input units designed for SoCs, providing image capture capability for mobile phones, digital still cameras (DSCs), tablets and netbooks with integrated cameras. The cores are available for 2D and for 3D applications. The high-performance camera pipeline features image processing, scaling and compression functions and is also capable of integrating additional features. The integrated image signal processor (ISP) supports simple CMOS sensors with no image pre-processing and sensors with integrated YCbCr processing.

The new Camera Processor IP core now supports 3D and high resolution still picture and video applications. camerIC-3D/64MP leverages production-proven technology to offer a cost-effective, low-power camera processor IP design that is compatible with common CMOS sensors to ensure ease of integration.

The camerIC-3D/64MP IP core supports resolutions ranging from 3MP up to 64MP (8Kx8K) in a single low-cost/low-power design. The IP core is supporting pixel rates up to 2x 300 megapixel/sec enabling high frame rates for high image resolutions.

To effectively deliver resolutions over 12MP, the camera processor features sophisticated bad pixel detection/correction and noise reduction techniques to ensure image quality even when paired with low cost, high-resolution CMOS sensors commonly found in mobile devices. The camerIC-3D/64MP IP core also supports wide dynamic range processing and digital image stabilization, along with an extensive set of standard features.

In addition to its DSC capabilities supporting up to 64MP resolution, the camera pipeline has the imaging bandwidth to support 3D 1080p resolution at up to 120 frames per second and more. 4Kx2K (8MP) resolution at 30 frames per second will require as few as 660k gates to implement in hardware while consuming as little as 125mW of power (40/45nm process). The camerIC hardware design is optimized to consume as little as 1 MIPS per frame of CPU bandwidth—making the camerIC-3D/64MP one of the industry’s highest performing, lowest cost/power camera processors.

The camerIC-3D/64MP IP core supports both parallel and serial input interfaces compatible with most CMOS sensors and several CPU and memory system interfaces. The CMOS sensor sends data to the ISP via parallel interfaces supporting ITU-R BT 601 and 656 compliant video data. In addition, several serial interfaces are supported including baseline compliant CCP-2 mobile imaging architecture (SMIA) and camera serial interface (CSI-2) MIPI. When communicating with a CPU or memory, 64bit AXI, 32bit AHB and BVCI/PVCI are supported.