The eSi-1650 16-bit CPU core is a low-cost, low-power processor with cache memory. The processor is targeted at application running from embedded or external flash memory. The addition of a cache will allow higher processor clock speeds and can greatly reduce the power compared to running from non-volatile or large memories.
Even though it is 16-bit, the gate count is equivalent to many 8-bit cores due to the simplicity of the RISC pipeline. With a wider data-path and 16 general purpose registers, application programs are able to execute in far fewer clock cycles. This can save a significant amount of power by either allowing the CPU to be clocked at a lower frequency or by being able to enter a power down state sooner.
For applications where high performance is required, the 5-stage pipeline allows extremely high clock frequencies to be achieved. While most instructions effectively execute in a single clock cycle, the deep pipeline allows the C and C++ compiler to schedule independent instructions such that instructions that can take multiple cycles to execute, appear to only take 1 clock cycle. Static branch prediction is employed to minimize the cost of branch instructions. Both of these features have until now only usually been found on high-end 32-bit CPUs.
For applications that require even more performance or require more memory than is catered for by the eSi-1650, the eSi-32xx range of 32-bit processors are available. These processors feature the same ISA as the eSi-1650, extended to 32-bits. The processor RTL and toolchain share a common code base, resulting in an easy migration path for both software and hardware developers, should the demands of an application change.
The toolchain for the eSi-1650 is based upon the industry standard GNU toolchain, which includes an optimising C and C++ compiler, assembler, linker, debugger, simulator and binary utilities. All these tools can be driven by the customizable Eclipse IDE (Integrated Development Environment). The debugger can connect to the target CPU either via JTAG or a serial interface. Complete C and C++ libraries are supplied. Port of FreeRTOS, Micrium uC/OS-II, Contiki and TinyOS are available. The toolchain is available for both Windows and Linux hosts and is available to use at no cost.
EnSilica is a quality provider of ASIC, FPGA and IP design service encompassing wired and wireless systems design, IP selection, low-power design and SoC integration, functional verification and silicon implementation. Application specific acceleration, peripheral design and software and tools development services can be offered to support product development using our range of eSi-RISC IP cores.
- 16-bit RISC architecture
- 16 general purpose registers
- 92 basic instructions and 10 addressing modes
- Supports up to 96 user-defined instructions
- 5-stage pipeline
- Choice of memory architecture:
- 64kB instruction and data (von Neumann)
- 128kB instruction and 64kB data (Harvard)
- Excellent code density
- Optional support for user and supervisor modes
- Up to 16 interrupts plus NMI and system call
- Fast interrupt response time of 6-9 cycles
- AMBA APB peripheral bus
- JTAG or serial debug
- Delivers 1.99 CoreMark per MHz
- ASIC Performance (Typical 0.13μm):
- Up to 600MHz
- From 8.5k gates
- 15 uW/MHz
- FPGA Performance (Virtex 5):
- Up to 160 MHz
- From 1100 LUTs
- High quality IP:
- Verilog RTL
- DFT ready
- Silicon proven
- C and C++ s/w development using license-free GNU tools, under industry standard Eclipse IDE