The Low Power Multi-Rate SerDes Includes all high-speed analog functions for a dual channel serializer and single channel deserializer and is optimized for low power operation at data rates from 584Mbit/s to 2.4Gbit/s. Alternative 10b and 40b input and output datapaths simplify design of link layers created from RTL using regular standard cells and regular synthesis, place and route flows. Excellent supply noise immunity in the CDR and TX PLLs makes the SerDes ideal for use in noisy mixed signal SoC environments.
- IP available with...
- Data rates of <200Mb/s to >8Gb/s
- Compatible with SGMII, SATA, FibreChannel, JESD 204, V-by-One
- Separate PLLs for Tx and Rx support a single reference clock or separate references from 20MHz to 400MHz
- Separate Serializer and Deserializer macros simplify assembly of arbitrary single- or multi-lane configurations
- 10bit and 40bit datapaths for easy SP&R of link layer
- Flexible driver and receiver circuits compatible with LVDS and CML standards with programmable low power settings
- IO library integrated to simplify integration and lower ESD risk
- Trimmable on-die termination ensures excellent signal integrity
- High-speed loop-back path simplifies production testing
- Comprehensive power-down control
- CDL Netlist (MG Calibre Compatible)
- Functional Verilog Model
- Liberty timing models (.lib)
- Application Note with integration and production test guidelines