The CL12491IP transmitter is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolution. The transmitter converts parallel 60bits (Dual Pixel 30-bit color) of LVCMOS data into serial 10-LVDS data streams. Control signals (HSYNC, VSYNC, DE) are sent during blanking intervals. The CL12491IP transmitter is an ideal means to solve EMI and cable size problems associated with wide, high-speed CMOS interfaces.
- -Input Clock: 20(40)MHz~135(270)MHz shift clock support
- -Output Clock: 20(40)MHz to 135(270)MHz
- -Output Data Rate: 140Mbps~945Mbps
- -Low power single 3.3V (Option: 2.8V)
- -TIA/EIA-644 and IEEE 1596.3 compliant
- -Clock edge programmable
- -Supports Dual Link and Single Link
- -Supports RGB 18 / 24 / 30
- -Narrow bus reduces cable size
- -PLL requires no external components
- -Power down mode
- -±345mV swing LVDS for low EMI
- -Supports 200mV Differential Amplitude Outputs
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP from this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file