The Recore many-core processor subsystem IP-on-FPGA connects Xentium DSP cores, a General Purpose Processor (GPP), and other IP blocks in a heterogeneous many-core processor architecture via a hybrid Network-on-Chip/AMBA bus inter-connect. The interconnect structure combines the best of both worlds: it promotes efficient data transfer via a Network-on-Chip (NoC) in the DSP subsystem, yet facilitates easy compatibility in a GPP subsystem with off-the-shelf general purpose processors (GPP), traditional IP blocks, and an AMBA bus.
To facilitate programming, the many-core processor subsystem IP comes with a Software Development Environment, a many-core functional simulator, and dedicated libraries. The Recore many-core processor subsystem IP-on-FPGA is instantiated on a Xilinx Virtex-6 FPGA.
- Up to 4 Xentium DSP cores (See Xentium Product Brief for details on the Xentium),
- 32-bit General Purpose Processor,
- Low-latency 512 kB SRAM memory tiles connected to the NoC and the GPP subsystem. The memory architecture depends on the selected instantiation,
- 32-bit packet-switched 2D Mesh Network-on-Chip based on 5-port routers with Quality of Service control; 1.9 Gbps (full duplex) link speed,
- Up to 7 NoC to AHB-Lite external IP interfaces,
- 16-pins GPIO,
- UART for data transfer and debugging,
- IP-on-FPGA system clock speed of 60 MHz.
- Heterogeneous many-core processor subsystem IP in various FPGA instantiations.
- Scalable Network-on-Chip connecting up to 4 Xentium DSP cores, memories, and up to 7 external IP blocks.
- Interconnect to AMBA bus system for compatibility to off-the shelf general purpose processors and common peripherals.
- Xilinx Virtex-6 board, pre-installed with the desired many-core processor subsystem IP configuration;
- Xentium SDE;
- Many-core simulator;
- Complete documentation set.
- Fault-tolerant applications for space, medical, and other markets requiring high reliability.
- Wireless communications and embedded vision.
Block Diagram of the Many-core processor subsystem IP-on-FPGA