The C387L implements a math coprocessor and is derived from the Intel® i387SX. The C387L extends the architecture of the Intel® 386 processor with floating-point, extended integer and BCD data types.
A computing system that includes the C387L fully conforms to the IEEE 754-1985 Floating-Point Standard. The C387L adds over 70 mnemonics to the instruction set of the Intel® 386, including support for arithmetic, logarithmic, exponential, and trigonometric mathematical operations. The C387L are upward object-code compatible from the 8087-math coprocessor and will execute code written for the i387DX and i387SX math coprocessors.
Typically the core is delivered as VHDL source code for ASIC implementations. The following options may be ordered according to user’s requirements:
- EDIF netlist for FPGA
- One-year maintenance
- On-site support
- High performance 80-bit internal architecture
- Implements ANSI/IEEE Standard 754-1985 for binary floating point arithmetic
- Fully compatible instruction set of i387DX and i387SX math coprocessors
- Implemented all i387SX architectural enhancements over 8087
- Full range transcendental operations for SINE, COSINE, TANGENT, ARCTANGENT and LOGARITHM
- Directly extends Intel®386’s instruction set to trigonometric, logarithmic, exponential, and arithmetic instructions for all data types
- Built-in exception handling
- Eight 80-bit numeric registers
- Expands Intel®386 data types to include 32-/64-/80-bit floating point, 32-/64-bit integers, 18-digit BCD operands.
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001)
- HDL RTL source code (ASICs) or post-synthesis EDIF netlist (FPGAs)
- Example C387L_CHIP. -- this design uses the C387L and illustrates how to build and connect memories DPRAM, Clock control unit and three-state buffer
- Sophisticated self-checking Testbench (Verilog versions use Verilog 2001) that instantiates example design C387L_CHIP, clock generator, process that stimulates external input signals, process that emulates the communication behaviour between processor Am386 and C387L, and process that compares your simulation results with the expected results
- A collection of C387L all reference bus transaction are captured of original AMD386 and Intel® i387SX device which are executed directly by the Test Bench
- Simulation script, vectors, expected results, and comparison utility
- Synthesis script (ASICs) or place and route script (FPGAs)
- Comprehensive user documentation, including design specification, verification specification, test plan, and a integration manual