The M8051 is a highly configurable softcore implementation of the industry standard 8051 microcontroller that features a clock-compatible twelve-clocks-per-machine cycle architecture. Use of standard synchronous design methodology makes this core simple to integrate into both ASIC and FPGA SoC designs.
- Binary and clock cycle compatible with Intel 8051 designs
- Classic 12-clock machine cycle implementation
- Separate data and code address spaces (Harvard architecture)
- 64Kbyte program and data address spaces
- 256 byte internal data memory address space
- Support for memory banking extensions
- Optional demultiplexed program and data interfaces.
- 5-input, two level interrupt controller
- 32 GPIO ports
- 2 16-bit counter timers
- Full-duplex serial port
- Flexible interfacing options for external peripherals
- Power saving modes: powerdown, idle and run
- The M8051 offers two power saving states. These are implemented by dividing the core logic into two synchronous clock domains using optional clock gates. These reduce power consumption by 75% in the idle state and to leakage levels in the powerdown state.
- VHDL '93 and Verilog 2001 RTL source code
- RTL configuration script
- VHDL and Verilog Testbenches
- Demonstration assembly code
- Simulation scripts for Modelsim and Cadence
- Synopsys synthesis compile scripts and UCF timing constraint files
- Mentor and Synopsys DFT and ATPG scripts
- Example netlist implementation with SDF files Detailed product specification and a user guide containing implementation notes