The CCWiMOFE00 is a low power and a low die-area AFE platform in 90nm CMOS technology for wireless broadband applications such as WLAN and WiMax. The AFE has been architected keeping in mind the scalability to more than one MIMO channel, supporting configurations such as 1x1, 2x2, 3x3, 2x1, 2x3, and so on.
The components of the AFE use architectures suited to nanometer technologies. A minimum number of amplifiers are used, thus making the implementation elegant and robust.
Its receive channel is based on a state-of-the-art ultra low-power and low-area 10-bit 80MSPS IQ-ADC core that enables keeping the active mode receive power down - useful in portable battery powered applications.The transmit channel consists of a 10-bit 80MSPS IQ-DAC pair.
The clocks for the ADC and DAC are generated by a versatile low jitter integer mode PLL integrated as part of the AFE. The PLL accepts commonly used wireless crystal frequencies of 13, 19.2, 26, 38.4MHz in addition to 20MHz and 40MHz.
An 8-bit 2$0MSPS auxiliary ADC that supports both single-ended and differential inputs is included, supporting multiple multiplexed analog inputs. An 8-bit 20MSPS auxiliary DAC is also included.
Three different power-states are available, namely, Suspend, Standby and Active. The AFE has been designed for low wake-up times from the Suspend and Standby states to Active state. The AFE does not require any external on-board components.
- Low-power & Low die-area MIMO AFE for Wireless broadband applications such as WLAN & WiMax
- Customizable to several MIMO configurations
- 1.2v Ultra low power IQ ADC
- 10-bit 80MHz IQ DAC
- 8-bit 20 MHz Aux ADC
- 8-bit 20 MHz Aux DAC
- PLL supports multiple input frequencies: 3Mhz, 19.2Mhz, 20Mhz, 26Mhz, 38.4Mhz & 40Mhz
- No external components needed for AFE
- Integrated band-gap reference
- Very Low receive power dissipation – ideal for battery-powered applications
- Wide Input common-mode range: 0.6V to 1.5V, for receive and transmit channels Fast wakeup from power-down and stand-by mode Power supplies: 1.2V ± 5% , 3.3V ± 10%
- Ultra Low die-area
- Optional LDO regulator: Input supply 1.62V to 3.6V , Output voltage: 1.2V
- Optional switching and linear regulators or powering digital, analog and RF components on-chip and off-chip
- Process: Fujitsu 90nm LL 6LM, 3.3V IO MOS process
- Status: Silicon proven in a 2x2 MIMO configuration test-chip