The CL12501IP Transmitter converts 18bits LVCMOS parallel data of RGB into 3-channnel mini-LVDS serial data streams. A Phase-locked transmit clock is transmitter in parallel with the data streams. The Cl12501IP transmitter is programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 112MHz, 18bits of RGB data are transmitted at a rate of 672Mbps per mini-LVDS data channel. The CL12501IP Transmitter is an ideal means to solve EMI and cable size problems associated with wide, high speed CMOS interface.
- Input Clock: 20MHz to 112MHz (max: 135MHz) shift clock support
- Output Clock: 60MHz~336MHz (max: 410MHz)
- Output Data Rate: 120Mbps~672Mbps (max: 810Mbps)
- Low power single 3.3V (Option: 2.5 / 2.8V)
- Clock Edge Programmable
- Narrow bus reduces cable size
- PLL requires no external components
- Power down mode
- ±200mV swing mini-LVDS IP for low EMI
- mini-LVDS format
- We uninvested form VC and other company now, so our IP can be very cheep.
- Our ASIC partner is GUC, PGC, Faraday, GSI.
- We can make Custom-IP from this IP.
- We are supplying circuits-macro for other IP license. And the customer can make hard-macro from circuits-macro.
- GDSII data
- SPICE netlist for LVS
- Timing models
- LEF file
- Verilog model
- Final simulation result
- Layout layer map file
- LVS and DRC log files
- Circuits data
- Simulation enviloment files
- IBIS or Hspice netlist file