The CCMIPIDPHY-T65LP integrates a MIPIŽ high-speed transmitter and receiver that supports up to 1GHz data transfer, and a MIPIŽ low-power transceiver that supports data transfer in the bi-directional mode. The IP supports the specifications described in v0.9 of the D-PHY spec. The digital D-PHY is integrated, and interfaces with the controller.
The architecture supports connection of multiple data lanes in parallel up to 4 data lanes can be connected to increase the total through-put. Customizable to user determined configurations, pairing with Cosmic Circuits MIPIŽ and low-jitter PLL. The foot-print is rectangular for any configuration.
Mixed-signal D-PHY mixed-signal hard-macro Transmitter and Receiver solution
Designed to MIPIŽ v0.9 Specifications
Integrated PHY Protocol Interface (PPI) supports interface to CSI, DSI and UniPro MIPIŽ protocols
1.0GHz maximum data transfer rate per lane
Expandable to support 4 data lanes, providing up to 4Gbps transfer rate