The MIPI DSI Receiver IP Core is used in mobile and high speed serial applications where a video or command data is sent using MIPI DSI Transmitter over MIPI lines to the MIPI DSI Receiver for decoding the data and use it for subsequent processing. The MIPI DSI Receiver along with the MIPI DPHY provides a complete solution for decoding MIPI data.
The MIPI Display Serial Interface (DSI) specification defines an interface between a peripheral device (Display or other data interface) and a host processor (baseband, application engine). This interface is defined by MIPI consortium, which defines a series of modules in a MIPI compliant product.
- Compliant with MIPI DSI Spec v1.1 and
- MIPI D-PHY Spec v1.1
- Max 1.5Gbps data transfer rate per Data
- Lane of DPHY
- Programmable 1, 2 or 4 Data Lane
- Operate in continuous and noncontinuous
- clock modes.
- Command and Video Mode are
- Burst and Non-Burst modes are
- Pulse and Event modes are supported.
- Configurable Virtual Channels upto 4.
- Supports all color modes -- 12, 16, 18
- and 24 bpp
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
- Design Guide
- Synthesis guide
Block Diagram of the MIPI DSI Receiver IP Core