The MIPI Alliance Specification for Unified Protocol (UniPro) specification defines a layered protocol for interconnecting Devices and components within mobile systems such as cellular telephones, handheld computers, digital cameras and multimedia devices. UniPro enables these devices and components to utilize MIPI PHY layers in order to exchange data at high data rates with low pin counts and at low energy per transferred bit. UniPro is applicable to a wide range of component types such as application processors, co-processors, modems, Camera, Display, and UFS and so on.
DME: DME module controls UniPro layer stack. This performs access to control information of local and peer devices and to reset the stack in ordered fashion and controls the power states of UniPro.
Transport Layer [TL Layer]: Interfaces with applications through CPorts and a maximum of 32 applications can interface with GDA’s UniPro controller. Round Robin arbitration scheme is used to handle the interaction with application.
Network Layer [NL Layer]: Routes the packet to the proper destination in a network environment by looking into the device ID code.
DataLink Layer [DL Layer]: Handles TC0, TC1 frames, group acknowledgement, preemption, retransmission and flow control of packets.
PHY Adapter Layer [PA Layer]: 20bit M-PHY interface and supports maximum of 4 data lanes. PACP generation and supports testmode.Also supports various power modes as defined by spec.
- Compliant with MIPI UniPro Spec v1.41.00, MIPI M-PHY spec v2.0.
- Programmable 1, 2 or 4 Data Lane Configuration.
- M-PHY HS data rates HS-G1,G2,G3 A/B and PWM data rates PWM-G1 to PWM-G7
- Supports End to End flow control.
- Supports traffic classes TC0 and TC1.
- Supports preemption of high priority frames.
- Supports maximum of 32 CPorts.
- Employs Round Robin arbitration across CPorts.
- Supports group acknowledgement of maximum 16frames per traffic class.
- Supports retransmission of frames.
- Configurable buffer spaces.
- Supports CSD, CSV.
- Supports UniPro Test Feature.
- TMPI Support.
- FPGA Validated.
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
- Design Guide
- Synthesis guide
Block Diagram of the MIPI Controller - UNIPRO