The CCMIPITXDPHY-T80GC integrates a MIPIŽ high-speed transmitter that supports up to 1GHz data transfer, and a MIPIŽ lowpower transceiver that supports data transfer in the bi-directional mode. The IP supports the specifications described in v0.9 of the DPHY spec. The digital D-PHY is integrated, and interfaces with the controller.
Supports MIPIŽ v0.9 Specifications
1GHz maximum data transfer rate
HS, LP and ULPS modes supported
LP-TX and LP-RX for bi-directional transmission in LP mode
Digital D-PHY integrated
Activates and disconnects termination for HS and LP modes automatically
Expandable to support 4 data lanes
Low Power dissipation: Contact email@example.com
Low Core Area: Contact firstname.lastname@example.org
TSMC 0.08μm 1P5M CMOS generic process -> IP uses 4LM
The IP is designed to support connection of multiple data lanes in parallel up to 4 data lanes can be connected to increase the total through-put.
Extra care is taken in ensuring the matching (both deterministic and random)
between the data and clock lanes allowing for very low skew between the two paths. The IP layout is done in such a manner that the IP is rectangular in shape for any configuration of data and clock lanes
resulting in no wastage in area when the number of data lanes is increased.
Video Demo of the MIPIŽ D-PHY compliant 1.0GHz Transmitter
Cosmic Circuits Demonstrating the MPHY's Tx and Rx performance in Lab
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