The MIPI D-PHY is used in mobile and high –speed serial applications where a MIPI lane is involved. The MIPI D-PHY adheres to MIPI D-PHY Specification. The The MIPI D-PHY along with the MIPI CSI Transmitter or CSI Receiver or DSI Host or DSI Slave provides a complete solution for encoding oe decoding MIPI data.
The MIPI PHY (D-PHY) specification defines an interface between the MIPI lanes and MIPI core engine like MIPI DSI or CSI. This interface is defined by MIPI consortium, which defines a series of modules in a MIPI compliant product.
- Compliant with MIPI D-PHY Spec v0.9
- Programmable 1, 2 or 4 Data Lane Configuration.
- Supports High-Speed and Low-Power modes
- Operate in continuous and non-continuous clock modes.
- Data Rate: 800 Mbps per lane on silicon (Spec mentions a max of 500 Mbps per lane) in High-Speed mode and 10Mbps in Low-Power mode.
- RTL code
- Detailed design document
- Verification environment
- Test cases
- Synthesis environment/scripts
- Design Guide
- Synthesis guide