The MIPI DigRF interface is a high speed, serial, digital chip to chip interface and communication protocol between Baseband processor ICs and RF IC enabling increased reliability, lower power, lower pin count and increased interoperability.
The low-power and area efficient DesignWare® 4G DigRF Master Controller implements all of the features defined for the protocol and PHY adaptation layers of the DigRF v4 rev 1.00 specification. The DesignWare DigRF IP has also verified interoperability with RFIC devices currently available on the market.
The DesignWare 4G DigRF Master Controller enables support for multiple standard air interfaces such as LTE and mWiMAX. It also provides flexibility for system-specific implementations, such as number of lanes and sublinks, diversity, IQ sample size, frame scheduling and handling of timing critical signals.
- Frame construction, serialization and scheduling in the Transmit channel
- Header decoding and payload processing in the receive channel.
- Configurable number of Rx and Tx Lanes
- Supports Low Speed (LS), High Speed 1x Primary (HS1P) and High Speed 1x Secondary (HS1S) modes;
- Configurable buffering FIFO size
- Configurable I/Q sample format
- Configurable Master Controller for MIPI DigRF v4 interface
- Compliant with MIPI Alliance Specification for DigRFSM v4 1.00.00 R0.03
- PHY interface compliant with MIPI M-PHY Signaling Interface
- Standard AMBA APB interface for configuration, control and status
- coreConsultant tool for single IP configuration, synthesis and simulation (GUI or batch scripts)
- Source Verilog RTL
- Automated synthesis using coreAssembler/coreConsultant, including support for DFT insertion and low power synthesis
- Comprehensive databook covering features, configuration, integration, software programmers guide and coreAssembler tutorial