MIPI D-PHY Receiver - TSMC 28 HPM

Features

• MIPI D-PHY RX solution
• D-PHY based on v1.1
• PPI supporting CSI-2 and DSI protocols
• High-Speed 1500Mbps data transfer per lane
• Modular implementation with lane scalability up to 4 lanes
• ULPS and Contention-Detection mode
• Uni- and bi-directional lane modes
• Low power dissipation
• Compact foot print
• TSMC 28 HPM process

Benefits

• Power and area optimized lane
• configurations for CSI and DSI solutions
• Optimized and matched analog design resulting in low clock-data lane skew
• Maximization of timing margins due to low skew between data and clock lanes
• Compact and rectangular foot-print even when scaled to different lane configurations
• Automatic termination control for HS and LP modes
• Built in sequence error detection for the receiver
• Integrated BIST capable of producing and checking PRBS, CRPAT and CJTPAT

Deliverables

• GDSII
• Netlist (Spice format for LVS)
• Footprint (LEF format)
• User documentation
• Module integration guidelines
• Datasheet
• Silicon validation report (where available)
• Evaluation board (where available)

Video Demo of the MIPI D-PHY Receiver - TSMC 28 HPM

Cosmic Circuits Demonstrating the MPHY's Tx and Rx performance in Lab