The MIPI DSI Device Controller is compliant to the MIPI DSI Specification Version 1.02 and, together with a MIPI D-PHY Version 1.0, offers up to a 4-lanehigh-speed/low powerserial connectivity between a DSI Host and the display panel. In command mode, for panels that contain frame buffers and display controllers, the DSI Device IP supports the DCS 1.02 command set over the DBI-2 interface. In video mode, for display modules without on-panel display controllers and frame buffers, the DSI Device IP supports pixel formats specified inthe MIPI DPI-2 specification.
Thus, Arasan DSI Device IP can support both DPI and DBI transactions over DSI. Using virtual channels, up to two DSI Device IP’s can be connected to Arasan’s DSI Host IP.
Features
- Compliant with the following MIPI specifications
- Display Serial Interface (DSI) version 1.02
- Display Pixel Interface (DPI-2) version 2.00
- Display Bus Interface (DBI) version 2.00
- Display Command Set (DCS) version 1.02
- D-PHY version 1.1
- DSI Host-side interface supports
- Connectivity to D-PHY through PPI Interface
- 1 to 4 data lane support
- Hi-Speed (HS) receive from 80 Mbps to 1.5Gbps per lane
- Low Power (LP) receive/transmit from/to host at 10 Mbps
- Continuous and stoppable clocks on clock lane
- Bus turnaround with contention and fault recovery
- Switching to and from Low Power (LP) and Ultra-low Power (ULPS) modes
- EOT, ECC, and CRC enable/disable mechanisms
- Multiple packets per transmission with interleaved data stream
- Acknowledge packets and trigger messages
- Programmable error injection in Verification IP and error detection in design IP
- Display Panel Connectivity and video/command processing
- DPI or DBI, depending on panel or display unit architecture
- Generic command support
- Generic parallel interface for sending and receiving vendor-specific information to and from the display driver logic in the display module
- Support for all generic read/writes over DBI/Generic interface
- Video mode support
- Supports wide range of display resolution and pixel formats
- Supported display resolutions: QQVGA, QCIF, QVGA, CIF,VGA,WVGA, XGA, 1080p, QXGA, QSXGA
- Burst mode and non-burst transfers over DPI interface
- DBI support
- Supports 8/9/16-bit data transfer in DBI TypeB interface
- Supports all DCS commands
- AHB Interface for register configuration and monitoring using programmed IO
Benefits
- Fully compliant to MIPI standard
- Small footprint
- Code validated with Spyglass
- Functionality ensured with comprehensive verification
- Product quality proven with silicon
- Premier direct support from Arasan IP core designers.
Deliverables
- Verilog HDL of the IP Core
- Synthesis scripts
- Verification environment
- User guides for design and verification
Block Diagram of the MIPI DSI Device Controller
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