MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pin counts combined with excellent power efficiency. As a MIPI Alliance contributor and leading Interface IP provider, M31 provides a silicon-proven and low-power M-PHY in different process nodes. The M-PHY IP follows MIPI M-PHY v3.0 spec and supports full range of high-speed (HS) and low-speed (LS) data transfer. Meanwhile, M31 provides M-PHY IP for both Type-I (UFS, DSI-2, CSI-3, LLI, SSIC, MPCIe) and Type-II (DigRF v4.0) applications.
It is compliant to the MIPI M-PHY RMMI interface which allows a seamless integrations with different upside controller.
- Supports MIPI M-PHY RMMI interface for UniPro protocol (UFS, CSI-3, DSI-2), LLI, SSIC, MPCIe (Type-I) and DigiRF v4.0 (Type-II) applications
- Optimized for High-Speed gears HS-G1A/B, HS-G2A/B and HS-G3A/B
- Supports Type-I ultra-low-power LS PWM modes from Gear1 to Gear7
- Reserved extension I/F of Type-II LS SYS burst mode for DigRF v4 application
- Supports LINE-CFG for Media-Converter
- Supports multiple signal amplitudes and slew rate control for EMI reduction
- Optimized power and area for multi-lane applications
- Compact IP size and easy for integrations
- Ultra low power consumption for both HS and LS mode
- Reliable BIST functions for production
Block Diagram of the MIPI M-PHY IP Core