This PHY IP can be configured as a MDDI Client or as a MIPI slave.
Depending on the mode of operation it is compliant with the VESA Mobile Display Digital Interface Version 1.2 specification and the MIPI Alliance Standard for D-PHY version 1.0.
It consists of 4 lanes: 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes, which makes it suitable for display interface applications.
The MDDI and MIPI blocks share the same signal and supply pins. The receive termination is embedded and can be used for both MDDI and MIPI. In order to meet the differential termination requirement for MDDI, the termination can be calibrated to cover sheet resistance variations. Once the Display module is qualified it can be used for both MIPI and MDDI resulting in faster time to market and in area and cost savings.
- Consists of 1 Clock/Strobe lane, 1 bidirectional data lane and 2 unidirectional data lanes
- De-serializers included
- Low power dissipation
- Built-in-test to enable production test
- Programmable receive termination
- MDDI features:
- VESA MDDI Version 1.2 compliant Client
- Operates up to 800 Mbps/lane
- Low Power Hibernation mode
- Programmable delay on strobe and data
- Programmable amplitude and common mode voltage for the reverse data driver
- MIPI features:
- Complies with MIPI Standard for D-PHY 1.0
- Supports both high speed and low-power modes
- 80 Mbps to 800Mbps data rate in high speed mode
- 10 Mbps data rate in low-power mode
- Data Sheet
- LVS Netlist
- Integration Guidelines
- Timing Model
- Behavioral Model
- LEF File for P&R