MIPI RFFE Master interface provides full support for the two-wire MIPI RFFE synchronous serial interface, compatible with RFFE specification. Through its RFFE compatibility, it provides a simple interface to a wide range of low-cost devices. MIPI RFFE Master IP is proven in FPGA enviroment. The host interface of the MIPI RFFE can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Wishbone or Custom protocol.
MIPI RFFE MASTER IIP is supported natively in Verilog, VHDL and SystemC
- Supports 1.0 MIPI RFFE Specification
- Full MIPI RFFE Master functionality
- Supports following frames
- Command Frame
- Data/Address Frame
- No Response Frame
- Supports extended register read/writes
- Supports Low power modes
- Supports half speed
- Supports baud rate control
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- SmartDV's MIPI Master IP contains following.
- The MIPI Master interface is available in Source and netlist products.
- The Source product is delived in plain text verilog or VHDL or SystemC source code
- Integration testbench and tests
- Scripts for simulation and synthesis with support for common EDA tools
- Documentation contains User's Guide and Release notes.