Motorola has developed and patented its Multiple Reference Clock Generator (MRCG) IP to meet the needs of SoCs that require real-time generation and control of multiple clocks running at different frequencies. The MRCG offers several advantages over traditional clock generation technologies such as phase locked loop (PLL) and direct digital synthesis (DDS). Deployed and proven in Motorola products, the MRCG is now available to SoC developers through IPextreme.
- Generates multiple output clocks, each with a programmable frequency and phase offset, from a single reference clock source
- Wideband operation—2 MHz to 1 GHz in 90-nm technology; higher frequencies are achievable in smaller technologies
- Output clock frequencies and phase offsets are programmable in real time through a serial programming interface (SPI)
- Can disable/enable or reconfigure any output clock in real time
- Deterministic behavior—output clock is stable 7 clock cycles after enabling the clock or re-programming to a new frequency or phase offset
- Area and maximum frequency of the MRCG scale with the target technology