The MPEG1/2 – Layer I/II Audio Decoder (CWda75) is an IP core designed to work as an engine for decoding audio streams. This IP core is supported on ASICs or FPGAs.
The IP core is implemented using the Coreworks proprietary FireWorks™ 32-bit RISC processor and the SideWorks™ reconfigurable accelerator.
The IP core commands, settings and state can be written/read by means of a configuration, control, and status register file, accessed by an AMBA APB interface. An external I2C, SPI, etc, core can be provided to drive this interface.
The IP core requires program and data memories which can be external or embedded in the chip. External cores can be provided to drive the Audio Data I/O interface to support audio formats such as SPDIF, I2S or TDM.
The codec configuration is provided via the Software Interface Protocol (SIP). The SIP is a composite structure with all the parameters required to encode or decode audio frames. The core may run continuously or frame by frame.
- Complete support of the MPEG1/2 – Layer I/II Audio specification
- Channel modes: mono, joint stereo and stereo
- Sample rates: Fs = 16, 22.05, 32, 44, 44.1 and 48 kHz
- Maximum 24-bit input audio resolution
- Requires 128 kB of external memory
- Best case latency Layer I (32 kbit/s): 200/Fs
- Worst case latency Layer I (448 kbit/s): 304/Fs
- Best case latency Layer II (32 kbit/s): 600/Fs
- Worst case latency Layer II (384 kbit/s): 864/Fs
- Configuration, control and status interface for commands, settings and state
- Supports AMBA-AHB master interface to memory controller, APB slave interface for Configuration, Control, Status and Programming interfaces
- Easy to use multi-channel parallel TDM interfaces
- Parallel audio interfaces easy to connect to industry standard interfaces such as AES3, SMPTE337M, SPDIF, I2S/TDM or custom interfaces
- Supports burst or continuous data flows
- Parallel boot interface easy to connect to industry standard interfaces such as SPI, I2C, etc.
- Real time operation @80 MHz
- Compact hardware implementation –fits economically in FPGAs
- Low operation frequency
- Extreme low power consumption
- Small external memory footprint
- FPGA netlist
- Program binaries
- Implementation constraints
- Evaluation board (optional)