Multi-Channel-OPB (MCH_OPB) SDRAM Controller

Features

• Parameterizable number of channel interfaces - each channel can be configured with a Xilinx Cachelink (XCL) protocol
• Optional OPB interface
• Performs device initialization sequence upon power-up and reset conditions
• Supports SDRAM self-refresh mode
• Performs auto-refresh cycles
• Supports single-beat and burst transactions
• Supports target-word first XCL cache-line transactions of 1,4,8, and 16 words
• Supports cacheline latencies of 2 or 3 set by a design parameter
• Supports various SDRAM data widths (8, 16, and 32 bits) set by a design parameter
• Operating frequency >=100MHz Min Max