The cineramIC-3D/4K Multi-Standard Ultra High-Definition Video Decoder IP Core is one of the highest performing synthesizable cores on the market capable of decoding multiple video streams in different standards. It is substantially more efficient to implement than fully programmable solutions and it achieves high performance levels at very low clock rates (e. g. one 4Kx2Kp@30fps or one 3D 1080p@60fps or two 1080p@60fps streams at 300MHz).
The cineramIC-3D/4K Multi-Standard Ultra High-Definition Video Decoder IP Core supports H.264, MPEG-1/2 and VC-1 video standards including H.264 MVC (Multiview Video Coding) and JPEG standards for still picture applications. Automatic multi-stream video decoding is supported for up to to 16 streams without additional software interaction. Driver software performs set up and general controlling tasks requiring fewer than 2 MIPS of CPU resources on common general purpose 32-bit processors.
This IP core reads the input stream from a buffer located in the system memory (SDRAM) and generates decoded video in YCbCr 4:2:0 and 4:2:2 (JPEG) formats. The output pictures are stored in the decoded picture buffer area within the system memory.
The cineramIC-3D/4K Multi-Standard Ultra High-Definition Video Decoder IP Core is optimized for video decoding applications based on an architecture that implements pipelining and parallelism on different levels. The cineramIC-3D/4K Multi-Standard Ultra High-Definition Video Decoder IP Core consists of both a software and a hardware component. The hardware is composed of two main blocks, the Stream Interpreter and the Multi-standard Video Decoding Engine. In order to achieve maximum performance, the two blocks work in parallel.
The cineramIC-3D/4K Multi-Standard Ultra High-Definition Video Decoder IP Core is optimized to satisfy a wide range of applications and technologies with optimal performance at low silicon cost and power. Its interfaces can be easily integrated into system-on- chip (SoC) designs.
- Supported standards:
- ITU-T H.264 incl. Annex H, MVC, ISO/IEC 14496
- 10 (Main and High Profile up to Level 5.1)
- SMPTE 421M VC-1 (Simple, Main and Advanced Profile @ Level 4)
- ISO/IEC 11172-2 MPEG-1
- ISO/IEC 13818-2 MPEG-2 (Main Profile @ High Level)
- Supports up to 4096 x 2160 pixel resolutions (4Kx2K)
- Supports 3D video
- Supports Exif JPEG up to 16Kx8K picture size
- Supports all DVTB, ATSC, HDTV, DVD, VCD resolutions (e.g. 1080p, 1080i, 720p, D1)
- Hardware supported context switching between video streams (configurable up to 16 streams)
- Error detection and concealment
- Trick mode support
- Processing of ES and PES streams, extraction and provision of time stamps
- Memory system can run with different clocks; clock domain crossing is part of the IP core
- Implementation for FPGA available
- Allegro H.264 certification test suite proven
- 64-bit ports to memory system, OCP 2.0 and AMBA AXI compliant
- Runs on TSMC 65G @ 350 MHz
- Silicon area and power efficient solution
- Driver software is included with easy to use API incorporates multi-stream / multi-standard control
- C source code, portable to any CPU
- Single-stream decode up to 4Kx2Kp @ 30 fps at 300MHz core clock frequency
- Single-stream decode up to 3D at 1080p @ 60 fps at 300MHz core clock frequency
- Dual-stream decode up to 1080p @ 60 fps at 300MHz core clock frequency
- Time multiplexed multi-stream decoding up to 16 streams, example combinations are:
- Four HD video streams H.264, MPEG-2, VC-1
- Two H.264 HD streams and eight MPEG-2, SD streams
- Exif JPEG decoding ~1 Mpixel/MHz, e.g. 8 Mpixel @ 38 fps or 32 Mpixel @ 9 fps at 300MHz core clock frequency
- Hardwired, autonomously running decoding pipeline, two samples per clock throughput
- Verilog RTL code with synthesis scripts
- Extensive verification environment
- Reference software
- Detailed user manuals for hardware and software
- Professional Video
Block Diagram of the Multi-standard and Multi-stream Ultra High-Definition Video Decoder (H.264, MPEG-1/2, VC-1, JPEG) with MVC Support for 3D Video Applications