The ARM Cortex-A9 MPCore multicore processor integrates the proven and highly successful ARM MPCore technology along with further enhancements to simplify and broaden the adoption of multicore solutions. The Cortex-A9 MPCore provides the ability to extend peak performance to unprecedented levels while also supporting design flexibility and new features to further reduce and control the power consumption at the processor and system level.
Targeted implementations of the Cortex-A9 MPCore can also offer mobile devices increased peak performance over today’s solutions by utilizing the design flexibility and advanced power management techniques offered by the ARM MPCore technology to maintain operation within the tight mobile power budgets.
Using the scalable peak performance, this processor is able to exceed the performance of today’s comparable high-performance embedded devices and brings a consistent software investment over an extended breadth of markets.
Both the Cortex-A9MPCore and the Cortex-A9 application-class processors are supported by a rich set of features and ARMv7 architectural functionality so as to deliver a high-performance and low-power solution across both application specific and general purpose designs.
- High-Efficiency Superscalar Pipeline
- Industry leading performance with over 2.0 DMIPS/MHz for unprecedented peak performance while also maintaining low power for extended battery life and lower cost packaging and operation
- NEONTM Media Processing Engine
- Accelerating media and signal processing functions for increased application specific performance with the convenience of consolidated application software development and support
- Floating-Point Unit
- Provides significant acceleration for both single and double precision scalar Floating-Point operations. Double the performance of previous ARM FPU, this unit provides industry leading image processing, graphics and scientific computation capabilities
- Optimized Level 1 Caches
- Performance and power optimized L1 caches combine minimal access latency techniques to maximize performance and minimize power consumption. Also providing the option for cache coherence for enhanced inter-processor communication or support of rich SMP capable OS for simplified multicore software development
- Thumb®-2 Technology
- Delivers the peak performance of traditional ARM code while also providing up to a 30% reduction in memory required to store instructions
- T rustZone® Technology
- Ensures reliable implementation of security applications ranging from digital rights management to electronic payment. Broad support from technology and industry Partners
- Jazelle® RCT and DBX Technology
- Provides up to 3x reduction on code size for Just-in-time (JIT) and ahead-of-time compilation of bytecode languages while also supporting direct byte code execution of Java instructions for acceleration in traditional virtual machines
- L2 Cache Controller
- Providing low latency and high bandwidth access to up to 2 MB of cached memory in high frequency designs, or design needing to reduce the power consumption associated with off chip memory access
- Program Trace Macrocell and CoreSight™ Design Kit
- Together these components provide the software developer with the ability to non-obtrusively trace the execution history of multiple processors and either store this, along with time stamped correlation, into an on-chip buffer, or off chip through a standard trace interface so as to have improved visibility during development and debug