With fiber to the home, node, basement, the functionality and the complexity of a Gateway Processor and Ethernet Switches increases significantly. The current generation gateway architectures in CPE are not addressing multi gigabit data rate with the growing functionality. These advanced architectures would need to
• Route Multi-Gigabits of data
• Provide sophisticated Quality of Service for applications like IPTV,
• Handle very high number of flows
• Ultra low cost device adaptable to mass markets
• Needs to be highly programmable for changing requirements
• Enable VPN, deep packet inspection to protect against attacks
The Wire-Speed Switching and Routing (WSP) Solutions are highly scalable and configurable for various applications, enabling network connectivity, switching and routing. The engines offer complete offload of TCP / IP processing at hardware level to achieve higher data rates without burdeningthe host processor.
The WSP Processor architecture guarantees wire speed secure routing of any size packets between Gigabit Ethernet ports. The architecture is highly scalable for multiple Ethernet ports or peripherals with other protocols like ATM and is scalable for GPON and GEPON architectures. The hardware/software partitioning and the partitioning of software between Host Processor and Embedded modules ensure that WSP software can be very easily integrated into customer’s existing software.
- 2 Gigabit Wire Speed Packet Processing
- Bridging with VLANs
- Routing with L3 and L4 fields
- Two Gigabit Ethernet Ports
- Efficient DDR-I/DDR-II SDRAM Controller
- Built in Buffer Manager for On-Chip Buffers and Off-chip Memory
- Flexible buffer/packet hand off to the host
- Hardware based QoS
- Multi-Processor based Classification.
- All dependencies are resolved with hardware
- Optionally IPSEC engine can be integrated into the data-path
- Hardware based Flow Control
- Very Simple Interface to the Host Processor
- Most of the processing in the Hardware
- Efficient trade-offs on S/W and H/W for small die size
- Working in an FPGA board with Linux OS and MIPS host.
- Verification Environment:
- 1. Verilog Test Bench.
- 2. System Verilog.
- 3. OVM.
- Fully Encrypted Verilog Synthesizable RTL
- Testbenches and Testcases.
- ASIC Synthesis Scripts
- FPGA Synthesis and P&R Scripts