The Xelic Multi-Rate LAPS Processor Core (XCL12M) contains independent Transmit and Receive Processor modules for STS-3/STM-1 or STS-12/STM-4 SONET/SDH frame data rate applications. Incoming/outgoing data is transferred with an input clock rate up to 100Mb/s using an 8-bit data bus.
The XCL12M Transmit Processor interprets incoming ethernet packets and performs rate adaptation through the insertion of rate adaptation sequence characters and LAPS frame flags. Incoming client ethernet packets are processed with valid and invalid packet detection provided. Invalid packets are optionally indicated in the LAPS frame through the insertion of an escape sequence or the inversion of the FCS field. Ethernet packets are encapsulated into generated LAPS frames. Address, control, SAPI and FCS field information is inserted into outgoing LAPS frames. Transparency is provided by replacing specific LAPS field information data with appropriate control sequence bytes. A configurable interframe gap is provided through the insertion of flags to achieve a specified spacing between LAPS frames. Diagnostics support includes optional continuous LAPS flag generation, test frame insertion, corruption of inserted FCS field information and scrambling enable/disable capability.
The XCL12M Receive Processor performs LAPS frame descrambling, delineation, and removes all flags including interframe gaps. Rate adaptation information is removed and transparency processing translates control sequence information and removes appropriate control bytes. FCS address, control, SAPI, and FCS fields are examined for errors and reported through external signaling. LAPS frame interpreters provide test frame detection, incoming flag detection, rate adaptation sequence detection, transparency sequence detection, FCS error detection, frame abort sequence detection, and invalid control sequence detection. Support is provided for configurable LAPS frame address, control, and SAPI field mismatch detection. A client FIFO interface is provided with Start of Packet (SOP), End of Packet (EOP), data valid, valid packet, and invalid packet signaling.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCL12M core available under flexible single use licensing terms with netlist or source code deliverables.
- Compliant with ITU X.86/Y.1323 Specification.
- Provides full duplex operation with independent transmit and receive functionality.
- Operates at data rates up to 622Mb/s (OC-12).
- Provides signaling for line side interfacing to SONET/SDH Framers.
- Supports configurable interframe gap capability.
- Provides configurable test frame insertion and continuous LAPS flag insertion options for test purposes.
- Calculates and inserts FCS with corruption capability for test purposes.
- Supports transparency and optional extended transparency processing.
- Performs rate adaptation through the insertion of Rate Adaptation Sequence (0x7ddd) and Flags.
- Provides LAPS frame invalid packet indication through configurable abort sequence insertion or FCS inversion.
- Provides LAPS frame Start of Frame (SOF), and End of Frame (EOF), interframe gap, rate adaptation, and transparency signaling indicators.
- Optional self synchronous scrambler/ descrambler operation.
- Performs delineation on incoming LAPS frames.
- Provides status signals for LAPS test frame detection, incoming flag detection, rate adaptation sequence detection, transparency sequence detection, FCS error detection, frame abort sequence detection, and invalid control sequence detection.
- Supports configurable LAPS frame address, control, and SAPI field mismatch detection.
- Provides client FIFO interface with Start of Packet (SOP), End of Packet (EOP), data valid, valid packet, and invalid packet detection signaling.