National Semiconductor I2S Audio Interface

The I2S Audio Interface provides a bidirectional, synchronous, serial interface to off-chip audio devices. It complies with the Inter-IC Sound (I2S) bus specification from Philips Semiconductor (I2S bus specification; February 1986, revised June 5, 1996) and is the same I2S Audio Interface IP proven in high-volume devices from National Semiconductor.

The host interface of the I2S Audio Interface complies with the AMBA 2.0 APB protocol. Control registers provide CPU control of master or slave mode, audio data format, data word length, bit clock generation, word select signal resolution, FIFO threshold levels, and enabling/disabling interrupts. Status registers provide interrupt and FIFO status.

Transfer of audio data to/from the host system can be either interrupt-driven or through DMA to reduce CPU utilization. In both cases, four 8-word-deep FIFOs with programmable threshold levels provide storage of transmit/receive data for the left and right channels. APB-accessible registers provide read or write access to each of the four FIFOs.

The I2S bus interface of the I2S Audio Interface is a set of unidirectional signals that connect to chip I/O pads to form the off-chip I2S bus signals: serial clock (I2SCLK), word select (I2SWS), serial data in (I2SSDI), and serial data out (I2SSDO). To reduce chip-level pin count, the I2S bus interface signals can be shared with other on-chip functions through a General Purpose I/O (GPIO) Controller.