The Near Field Communication (NFC) IP core uses a patented digital signal processing, or DSP based transceiver architecture. This makes this IP core easily portable across multiple technology nodes and easily tunable to work with different types of antennas.
The IP transceiver is divided into two sections. The first section, the AFE, features the transmitter, receiver and card detection logic. These are delivered as hard macro in GDS format. The digital section implements link-control logic with an AMBA APB interface with the host controller. Theae are delivered in register-transfer level (RTL) code. Both reader mode and card emulation mode are supported by the IP.
- Uses a proprietary and patented digital NFC architecture. No mixers, No active analog filters, No PLL, No DLL but a lot of low power digital filters.
- Extremely easy antenna tuning: No tuning registers; all sensitive analog blocks are automatically calibrated; Transmitter tr/tf is digitally programmable
- Powerful and digitally programmable transmitter; does not need RF booster
- Transmitter power and signal slope are digitally programmable
- All offsets (such as comparator offsets) are digitally auto-calibrated
- Clock frequency is digitally calibrated
- Sensitive receiver with Auto SNR tuning
- Much faster antenna tuning, compared with other analog-based solutions.
- No need for external power booster/amplifier
- Easy portability to different foundry processes and geometries
- Evaluation boards available
- GDS for AFE
- RTL for link control
- SDC for synthesis constraints
- Verilog + Ruby based test bench
- IP Integration Guide
- Altera Cyclone III based RTL for verification
- POS, mPOS, payment processing
- Internet of Things
- Access Control
Block Diagram of the Near Field Communication AFE