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NVM express controller IP Core

The NVMe Controller and driver provide application layer support for processing NVMe commands. It is situated between a PCIe Controller and Flash Memory Controllers to provide the data transport required for SSDs. It provides an autonomous Queue Management system to fetch NVMe commands from Host Memory without local firmware processing. Individual or multiple data blocks are then transferred by DMA within the NVMe Controller when local firmware or additional hardware indicates the availability of the Flash resources. The Queue Management system retains enough information about the NVMe command queues to reduce the overhead of continually accessing Host Memory other than for block data transfer.

The design is highly configurable allowing many aspects of the Controller to be customized according to system requirements. Features such as the number of command queues supported, size of each queue, maximum number of outstanding commands are all definable at RTL Compile time. The design can be supplied with Industry standard system buses or with a FIFO interface to meet specific needs.

Features

Supports NVM Express Standard Revision 1.0c.
The number of I/O Queues supported can be configured up to the maximum of 65536 Queues.
The size of each I/O Queue supported can be configured up to the maximum depth of 65536 Commands.
Supports a maximum of between 10 and 2000 outstanding commands at any one time.
Admin Queue commands to create or delete I/O Queues are handled autonomously without local firmware support.
Block read/write data is transferred with low overhead.
Full support of Host Memory page size from 4 Kbyte to 128MByte.
Support for Weighted Round Robin with Urgent Arbitration Mechanism.
Tiered Data Support
Administrator command support
Support for MSI and MSI-X PCI Interrupt mechanisms. The number of MSI-X Interrupt vectors available (MSI-X Table Size) is configurable.
Full support for memory mapped NVMe Registers.
Support PCIe features such Bifurcation, SRVIO, MIMO and others

Benefits

The NVM Express 1.0c specification defines an optimized register interface, command set and feature set for PCI Express Solid-State Drives (SSDs). The goal is to help enable the broad adoption of solid-state drives (SSDs) using the PCI Express (PCIe) interface.”NVMe is the latest interface standard to enable flash to obtain performance that has been unachievable with existing standards. Offering possibly the lowest latency and greatest number of pipeline and parallel command processing capabilities. Cadences NVMe IP is one of the first in the industry with the highest performance and coupled with a firmware driver to get your product to market with confidence and flexibility

Deliverables

Readable and commented RTL, fully regressed by Cadence for each delivery
User Guides and Documents
Synthesis Scripts and STA scripts
Basic Test Bench
Firmware stack in C source code
Software users manual

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