ONFI 1,2,3/ Toggle 1,2 Nand Flash controller for All major NAND interfaces and devices. Low latency silicon proven.

Features

• SLC or MLC, supports all boot operations and ID access
• Supports ONFI 1,2,3/ Toggle 1,2 NAND
• Synchronous or asynchronous device operation
• Configurable Bank/Chip select and Volume support options
• Page sizes of 512 bytes, 2 Kbytes, 4 Kbytes, 8 Kbytes and 16Kbytes.
• Optional multi-bit cell ECC (2 to 100+-bit correct BCH code)
• Error logging with ECC and detection
• Device specific ECC on/off control
• Error interrupts and error locator circuits
• Reduces Semaphore redundancy
• Supports all NAND command accesses
• Access to spare data space in NAND device
• Data and Command DMA available
• OS support, Linux, embedded Linux, Windows CE, and Mobile
• Read/Write Cache Command support
• Multi Plane operations
• Partial Page acceleration
• Posted write buffers
• Supports Erased Page detection in HW
• Multiple low-power options
• Context Switch Command DMA
• Support for CRC-32 and CRC-64 page granularity
• Sector mode reads (with ECC protection). If host wants to read only a few sectors of an entire page, it need not read the entire page, but can just read the desired amount.
• PHY availability for Both ASIC and FPGA
• Supports ONFi 2.3, 3.0, Toggle 1,2 volume support
• Sector mode reads (with ECC protection). If host wants to read only a few sectors of an entire page, it need not read the entire page, but can just read the desired amount.

Benefits

• Silicon proven with 250 design wins and 100 designs in silicon, spanning 27 vendor process nodes 1,2,3/ Toggle 1,2 NAND Flash Memory Controller IP MLC/SLC/TLC ECC BCH high performance. The lowest latency data path along with compliable ECC solutions optimized for your solution. Command DMA and optimized command pipeline reduce SW development as well as improve performance. Capable of working with the same controller from Asynchronous interface all the way to the maximum mode for ONFI 1,2,3/ Toggle 1,2 NAND.

Deliverables

• Deliverable include: synthesize RTL source for ASIC applications or netlist for FPGA target.
• Implementation is supported with a complete system-level test-bench and NAND device models, performance analysis routines, synthesis and static timing scripts, and comprehensive documentation.

Block Diagram of the ONFI 1,2,3/ Toggle 1,2 Nand Flash controller for All major NAND interfaces and devices. Low latency silicon proven.