The ONFI 3.0 Nand Flash Controller is a flexible high performance soft IP core capable of interfacing with NAND Flash devices fully conforming to the latest Open NAND Flash Interface Working Group (ONFI) 3.0 specification. ONFI 3.0 presents a clear evolutionary path to the NAND Flash storage by providing synchronous modes to achieve higher throughputs and to support higher density memories.
The Controller architecture is very generic and highly modular to address customer specific requirements with generic AXI/AHB/APB/FIFO interfaces . The IP supports NAND flash accesses up to 400 MTPS (Mega Transfers per second) with transfer size of 8bits or 16 bits depending on the mode of operation. To avoid data throttling on the Host processor side the IP core has an internal 16 deep Data Buffer which can queue up to 16 commands.
- Compliant to ONFI3.0,AMBA AHB 2.0, APB 3.0, AXI 2.0
- Supports different formats such as Hynix, Micron, Samsung,
- SanDisk, Sony Corporation, Spansion
- Support Toggle Mode
- Backward compatible with ONFI 2.2/1.0 specification
- Asynchronous [0-5] and Synchronous [0-5] modes of operation.
- Supports SDR modes[0-5], NV-DDR modes[0-5] and NV-DDR2 modes[0-7]
- Supports both SLC and MLC NAND flash memories.
- Supports Hamming Code and BCH code (up to 40bits error correction).
- Programmable page size 512B, 2KB, 4KB, 8KB, 16KB.
- Configurable FIFO depth - typical (256 x 32)
- Supports ECC Enable and Disable options
- Programmable Access Timing
- Programmable Row ( 1- 4Bytes) and Col Address Cycles (1-4Bytes)
- Supports NAND flash accesses up to 400 MTPS
- Supports up to 8 Banks.
- Supports single, INCR4, INCR8, and INCR16 Burst mode of operation
- Supports Multiple LUN Operations,Interleaved read, page program, and erase operations.
- Internal DMA Engine for Boot code transfer.
- Backward compatible with prior standards such as ONFI 1.0 and 2.2.
- Boot strap option: Support up to 8KB page size for boot.
- Customizable boot options
- Data Transfer Modes: Boot, XIP, PIO, DMA Modes.
- All mandatory commands and most of the optional commands
- Warm up cycles for data input and data output
- Complete access to spare area
- One Engine supports Multiple Devices
- Lowest Gate Count
- Complete Solution IP, HW & SW Development Kit
- Lowest Power / Highest Performance at System Level
- Internal DMA for Boot code transfer
- Customizable boot options-Supports Automatic Booting
- Highly Configurable IP
- World class customer support
- Fully synthesizable RTL Code
- Unencrypted Source Code
- Self-checking Test bench and Testcases
- Verification specification
- ASIC/FPGA synthesis scripts
- Simulation Scripts NC Verilog, VCS , ModelSim , QuestaSim
- User documentation
- Integration manual
Block Diagram of the ONFI 3.0 Nand Flash Controller