The ONFI 3.0 NAND Flash Controller IP Core supports the Open NAND Flash Interface Working Group (ONFI) 3.0 standard and is backwards compatible. It uses differential signaling on the clock and data lines and clocks at any frequency up to 200 MHz.
The ONFI 3.0 NAND Flash Controller is a full featured, easy to use, synthesizable design that is easily integrated into any SoC or FPGA development. Designed to support both SLC and MLC flash memories, it is flexible in use and easy in implementation. The controller works with any suitable memory device up to 128 Gb from leading memory providers such as Micron, Samsung, Toshiba, Hynix, ST-Micro, and others.
The IP core includes a host of configuration options from page size to band selects. The controller offers Hamming Code (1bit error correction and 2bit error detection) and BCH (option for 4-, 8-, 12-, up to 64 bit error correction) error code correction (ECC) for optimized performance and reliability. Additional features include the capability to boot from flash.
The controller supports a variety of host bus interfaces for easy adoption into any design architecture. An optional NAND Flash file system is available to support advanced features. The file system converts complicated tasks of NAND flash memory interfacing to simple memory accesses. Flash memory read, write, garbage collection, bad block management, and other functions are handled by the file system in the background.
The cores are delivered in Verilog RTL that can be implemented in an ASIC or FPGA. They are fully tested with vendor models and hardware tested with FPGA-based HDK products. The core includes RTL code, test scripts and a test environment for complete simulation and verification.
- - Compliant to ONFI revision 3.1 standard
- - Supports NV-DDR2 mode of operation supporting up to 200MHz
- - Supports NV-DDR mode of operation supporting up to 100MHz
- - Supports legacy Asynchronous devices operating from 10MHz to 50MHz
- - Can be used with any other ONFI digital controller
- - Supports 1.8V/3.3V operation I/O pads complaint to ONFI 3.1
- - Contains a PLL to support all frequencies from 10MHz to 200MHz
- - Uses 2X clock for better timing
- - Dynamically center aligns the DQS for better noise margin and immune to PVT variations
- - Supports differential signaling of DQS and RE signals
- - Supports four levels of drive strength as mentioned in the ONFI 3.1 standard
- Fully compliant, silicon-proven core
- Premier direct support from Arasan IP core designers
- Easy-to-use industry standard test environment
- Unencrypted source code allows easy implementation
- ReUse Methodology Manual guidelines (RMM) compliant verilog code ensured using Spyglass and OVM
- • Verilog HDL of the IP core
- • Test environment and test scripts
- • Synthesis scripts
- • Sample ARM firmware and software drivers
Block Diagram of the ONFI 3.1 NAND Flash Controller for Device