The Xelic Optical Transport Network (OTN) 100G Framer Core (XCO4) performs Optical Channel Transport Unit (OTU), Optical Channel Data Unit (ODU), and Optical Channel Payload Unit (OPU) overhead/data processing, aligns incoming OTU4 or ODU4 frames, and provides overhead interpretation with error detection and performance monitoring. The XCO4 contains independent transmit and receive processors with external ports for overhead insertion and extraction with support for ODU4 streaming and payload mapping modes of operation. Delay Measurement capability is provided in both Transmit (PM/TCMi) and Receive (TCMi) processors. Client and Line side data transfers use read enable and data valid signaling at clock rates up to 180 MHz to allow for flexible system clocking schemes. A flexible data bus architecture is used for ODUk/OTUk transport to provide 640-bit transfers for FPGA applications and 320-bit transfers for ASIC implementations.
The XCO4 Transmit Processor inserts OTU4, ODU4, and OPU4 overhead, calculates and inserts parity, automatically generates Backward Defect Indication (BDI) signaling, and scrambles generated frames. Support is provided for generic mapping procedure (GMP) justifications. Programmable Trail Trace Identifier buffers are implemented for Section Monitoring (SM), Path Monitoring (PM), and Tandem Connection Monitoring (TCMi) overhead insertion. The XCO4 supports up to 6 levels of tandem connection overhead insertion and interpretation. Diagnostics support includes optional corruption of inserted parity and maintenance signal insertion. Programmable payload support includes asynchronous, bit synchronous, GFP, null test, and PRBS mapping types.
The XCO4 Receive Processor contains a configurable frame alignment unit with programmable options for OOF/OOM and LOFLOM algorithm state transitions. Incoming OTU4 or ODU4 frames are descrambled (optional) and aligned for OTN overhead processing. OTU4, ODU4, and OPU4 overhead information is extracted to both internal register locations and an external overhead port. Frame alignment signal overhead is interpreted to detect and report various conditions which include OOF, OOM, and LOFLOM. Support is provided for generic mapping procedure (GMP) justifications. ODU AIS, ODU LCK, ODU OCI and client generic AIS maintenance signals are detected with optional interrupt generation. FTFL and up to 6 levels of TCM insertion is provided. OPUk payload type mismatch error conditions are detected and support is provided for programmable payload type accept and inconsistent thresholds.
Performance counters (configurable for error sync mode) are provided for the accumulation of inserted (XCO4 transmit processor) and detected (XCO4 receive processor) positive and negative justification events along with BIP-8 parity and BEI errors for OTU SM, ODU TCMi, and ODU PM (XCO4 receive processor). Counters are configurable for saturating latch and clear operation or periodic error sync auto-update mode.
The XCO4 provides facility and terminal loopback modes of operation using Transmit and Receive Processor data path configurations for system debug purposes.
A 16-bit generic register interface for access and configuration of internal memory mapped locations is included.
- Suitable for FPGA and/or ASIC implementations.
- Integration support and maintenance available.
- XCO4 core available under flexible single use licensing terms with netlist or source code deliverables.
- Implements flexible data bus architecture.
- Provides for streaming and payload request modes of operation.
- Implements 16-bit register interface for programming of internal registers.
- Complies with ITU-T G.709 and ITU-T G.798 specifications.
- Supports transmit and receive facility and terminal loopback configurations.
- Support is provided for generic mapping procedure (GMP) justifications.
- Xelic cores are optimized to keep resource utilization low enabling designers to include more functionality in a single FPGA implementation.
- Xelic offers flexible licensing terms with single use, source code options available.
- Xelic cores come complete with a database which contains RTL source, a verification environment (generators, checkers, models, etc), an extensive suite of self checking tests, synthesis scripts, and a comprehensive set of core documentation (product brief, datasheet, fact sheet, etc.).